Recently, DDR (Double Data Rate) memories have been widely used in a variety of digital equipment including a personal computer and a server. Since a DDR memory has an independent clock signal, and transfers a data signal between the DDR memory and a memory controller at a high speed, it is necessary to transmit the clock signal and the data signal in synchronization with each other. Further, since the DDR memory transfers the data signal between the DDR memory and the memory controller at a high speed, it is necessary to equalize delay times (propagation times) in signal wires. A conventional DDR memory employs equal-length wires (equal-delay wires) in which wire lengths of signal wires are equalized using wires in a so-called meander shape, in which signal wires are serpentine, to equalize delay times (propagation times) in the signal wires.
Japanese Patent Laying-Open No. 5-275960 discloses a chip delay line for adjusting the wire length of an equal-length wire. The chip delay line has a tri-plate structure obtained by sandwiching both sides of a signal wire formed as a serpentine pressed film pattern between high dielectric layers, sandwiching both sides thereof between low dielectric layers, and further sandwiching both sides thereof between ground electrode patterns.